Anritsu MP1764C

Today’s demand for transfer of large amounts of data, such as video, over the internet, is resulting in expansion of high-speed transmission circuits and other infrastructure. In addition to the previously used STM-64/OC-192 (9.95328 Gbit/s) standards, we are also seeing use of 10.709225 Gbit/s (OTU-2), which includes FEC coding, as well as 3.125 Gbit/s x 4 and 10.3125 Gbit/s in 10 Gbit Ethernet. Furthermore, the Fibre Channel file transfer protocol at 4.25 Gbit/s is also coming into actual use. As these new standards are settled upon, there is an urgent need to be able to support evaluation of devices and circuits at these higher bit rates.

Our MP1763C Pulse Pattern Generator and MP1764C/1764D Error Detector are a BERTS (Bit Error Rate Test Set) supporting evaluation and testing of transmission equipment, high-speed devices, optical modules, etc., at every stage from R&D through to manufacturing and production at speeds from 50 Mbit/s to 12.5 Gbit/s.

High-speed And Wide Band One MP1763C/MP1764C can cover the band from STM-0/STS-1 to 10 Gbit Ethernet, STM-64/STS-192, OTU-2 and can be used with 4.25 Gbit/s Fibre Channel Systems.

Many Patterns

• 8 Mbit programmable pattern (corresponding to six frames of STM-64/STS192)
• PRBS patterns from 27 – 1 to 231 – 1
• PRBS pattern with randomness and mark ratio variance for rigorous testing
• Alternating pattern The MP1763C alternately sends normal and alarm patterns to a device for response testing.
• Zero substitution pattern This feature is effective for testing the clock regeneration of a 3R repeater.

Location Changeable Pattern Synchronization Trigger This feature makes it simple to monitor the waveform at any point in a long word pattern.

• High Q factor A high Q factor can be obtained by back to back connection (typical value at 10 Gbit/s, PRBS 223 – 1: 40 dB).